                                          GENERAL
The DMA handles the bulk of memory transfers in Playstation2. There are 10 DMA channels 
handling the memory transfers to and from the different targets. The operation of each channel 
is similar. The DMA reads 1 qword from the source memory pool and transfers it to the target. 
It then updates the internal counters and loops ,if necessary.

                                        DMA CHANNELS
Channel No. Channel     Register memory address
Channel 0 - VIF0  10008000
Channel 1 - VIF1  10009000
Channel 2 - GIF         1000A000
Channel 3 - from IPU    1000B000
Channel 4 - to IPU      1000B400
Channel 5 - SIF0  1000C000
Channel 6 - SIF1  1000C400
Channel 7 - SIF2  1000C800
Channel 8 - from SPR    1000D000
Channel 9 - to SPR      1000D400

                                          REGISTERS
Name  Meaning                       Usage                         Memory address
CHCR  Channel Control register      Control register. Handles :               00
                                     Start \Busy ,
                                     direction   ,
                                     mode     ,
                                     TIE      ,
                                     TTE      
MADR  Memory address                Address of DMA packet quadraword accessed       10
QWC   Quadra-word counter           Qwords remaining in DMA packet                  20
TADR  Tag address             Address of current DMA packet's DMA Tag               30
ASR0  Assembler Reserved 0                                                          40
ASR1  Assembler Reserved 1                                                          50
SADR                                                                                80

                                      CHCR BIT ENCODING
 _____________________________________________________________________________________________
|31|                                                          | 08  |07 |06 |05|04|03|02|01|00|
|  |                                                          |start|TIE|TTE|mode |Unkwn| dir |
|  |                                                          |     |   |   |     |     |     |
Field Meaning                 Usage
start Start operation         DMA operation switch    0 No operation
                                                      1 Start operation
TIE   Turned to 0
TTE   Tag transfer enable     Whether the first part of DMA data should be packed in with the 
                              qword containing the DMA tag
mode  Mode selector           Control the DMA transfer mode       00 Chain
                                                                  01
                                                                  10
                                                                  11
Unkwn Unknown                 This element is set to 01 for VIF DMA transfers
dir   Direction               DMA transfer direction  00 to memory
                                                      01 from memory
Bit 31 could be busy bit (for when DMA is within Packet ,not on a tag)

                                    DMA COMMON REGISTERS
Name  Meaning                       Memory address
CTRL  Control register              1000E000
STAT  Status register               1000E010
PCR   Position counter register     1000E020
SQWC  Stored quadraword counter     1000E030
RBSR                                1000E040
RBOR                                1000E050
STADR                               1000E060

Last updated
20/10/2001
